RF Principles for PCB Design

"You're telling me the path of least impedance and the shortest path are not the same in a conductor?"

Goddamn, another day where RF doesn't make any sense. 

But don't worry, once you hear the basic explanations, it becomes a lot easier to wrap your head around it and it's surprisingly logical. I'm going to divide this whole post into a few key concepts that need to be applied to any RF layout you make if you want it to properly work.

DC vs AC Signal Paths

Let's say you have a 2 layer PCB, where the top layer has all your signals travelling in normal traces, and the bottom layer is a GND plane. 

So, Electronics 101, any electronic signal in a circuit that travels in the signal trace to a component must return back to the source through GND. Simple, easy. The path it takes back to the source is called 'return path' - yes this has a proper name even though it's like the first thing you learn in electronics, because people figured out it is super important to consider in high frequency circuits. 

From what we know, a signal will always follow the paths of lowest impedance, and at low frequencies, your impedance is just your resistance - if this confuses you, read the other post relating to RF Basics. If you have a sheet of metal, so electrons are free to move anywhere in it, then you'll find that the path of least resistance taken by the electrons is ALWAYS the shortest path distance; and that makes sense if you remember this equation: (R = ρL/A); increasing the length of the conductor will increase the overall resistance.

Someone made a neat diagram that shows how a visualisation of that on a PCB:

Well, the rule hasn't changed; any signal will still "follow the path of lowest impedance "- Ah, right. Impedance.

As your frequency increases, you can't assume that your impedance is still just the resistance. Now, you have to consider the inherent inductances of the traces and capacitances the surrounding environment have which count towards the reactance part of the impedance. Those will influence your signal path and it starts to get really hard to predict where your signal wants to go exactly.

So, if we can't predict where the signal goes, how can we ever accurately design systems for high frequency stuff?
Well, hold on, there is a way we can introduce some predictability back to the process by standardising certain aspects of a PCB design. I'll list out some standards that are important to stick to, and then proceed to show you what the simulation above looks like at high frequencies:

1. Always have a GND plane right next to any layer carrying high frequency signals

Now this needs a fundamental understanding of an AC signal and how it propagates in order for the following explanation to make sense. You need to stop thinking in terms of circuit current flow and start thinking in terms of electric fields and where they go to. In steady-state DC, it's easy to imagine the current flow, a simple constant flow in one direction from the source to GND.

An AC signal that travels in both directions at a certain frequency (i.e. 50Hz signal changes directions 50 times in a sec) is different in concept. The electric field alternates its polarity over a time period. You can visualize this effect as inducing a subtle wiggling motion in the electrons between the potential of GND and the source. This type of diagram, which you may have encountered in almost every single non-RF lecture, serves as a representation:

But this diagram is incomplete and explains nothing about the behaviour of AC signals in the real world. 

Simply based on this diagram, you would assume and internalise that an AC signal only oscillates through the power supply and load, considering it is a closed loop circuit. After all, according to basic physics, current cannot appear out of nowhere, right? 

Nice try, electrons don't care about your feelings.  AC will literally 'wiggle' to anything around it that it can. At a certain point, AC sees everything as a circuit and stops caring about your cute little closed circuit diagrams. Have a look at an adjusted diagrams:

The blue sine wave specifically represents the general movement of electrons between the two branches, and the idea can similarly be represented by the 'wiggling' arrows between V+ and GND. Now bear with me, the next diagram might induce vomiting and panic attacks, but I promise I didn't forget my schizophrenia medicine or anything:

What the hell is happening, why and how is AC connecting to GND? Well, say hello to Mr. Farad. This is a type of 'coupling capacitance' and just means that AC starts to consider anything between two metals as a dielectric, which makes everything a capacitor - and AC loves capacitance; like you're technically a capacitor (too bad you you can't store intelligence, like you can store charge).

So, imagine for a second that you flip the ON switch for the AC signal. What happens in the following nanoseconds?
The electric field of the signal starts forming from the supply side and propogates through the trace. As it is propogating, the field is ALSO coupling with the GND plane right underneath it due to this capacitance. So, that means that current actually starts flowing in both the signal trace AND the GND plane under it at the same time. Take a look at this animation to clarify things a bit more. If you want an even more in depth explanation, then take a look at this 50 min video.

If this is all confusing you, then please takeaway one main thing from all this bullshittery: 

An AC electric field will try to couple to its return path. If there is no clear return path for the signal, then it will freak out and couple to everything it can see around it.

If you add a big GND plane under your signal, then you 'clamp' your return path to be right under the signal, as that's the easiest path for a capacitance to form; so almost all of the return path will be directly concentrated under the AC signal to make a nice line of coupled capacitance. You also have to control inductance, which I will get to in the following points. But baby steps...

Another point to add to this, is that if you ever have two signals and they have intersecting return paths, then you've fucked up, big chief. If you cross return paths, you no longer know which signal proportion exactly is going where and you'll start to get weird behaviour. Kind of like if you have a parallel branch in a circuit with unknown impedances on them. The current will split across the branch in unknown proportions etc.
An example of how this can happen is if you have a stackup of: Signal, GND, Signal - if you have two signals that share the same GND plane, then if two signals cross over each other, their return paths would intersect and there would be issues there.

From what I've just explained here, you could also deduce another high speed rule, which is to always route high frequency signals with sufficient distance to each other so they don't couple and add noise to each other.

Right, so with those explanations in mind, the following diagram should now make complete sense:

2. Always control trace impedance for high frequency signals

We've talked about RF reflections (omg, it's the site name) in the RF Basics post and essentially this is an application of that. If the signal trace isn't impedance matched to the load impedance then you'll start running into signal integrity issues especially as you get into higher rise time signals. So always check what the standard impedance of the track needs to be to match the load/source. The importance of this is much more apparent at faster rise time signals; refer to the post regarding rise times where I go through that concept.

Impedance matching a PCB trace above a GND plane is very straightforward since it's basically a microstrip transmission line. There are tons of online calculators available for this purpose, and you also have programs like Saturn PCB (which NASA used) that provide a multitude of built-in calculators catering to various PCB aspects. For RF traces that are particularly sensitive to interference, I would recommend looking at CPWG microstrips. This configuration involves a microstrip line surrounded by a stitched ground pour, which offers excellent shielding. Be careful, as the the gap between the ground pour and the microstrip has a direct effect on the characteristic impedance of the trace, so use the appropriate calculators.

If you know you're going to be controlling your trace impedances, then it's important to think about the stackup you want to use early on in the design process. Depending on the dimensions of the chosen stackup, the impedance-matched trace may end up being either very thin/thick. So, look at your manufacturer and their standard stackup configs then pick one that avoids you ending up with overly small/large impedance controlled traces. Personally, for the PCBs I've made, I always try to aim for reasonable widths in the 8-15mils range.

3. If possible, don't route a high frequency signal through one VIA, and DEFINITELY do not route it through multiple VIAs.

Sometimes, you just can't avoid a via because of shitty layout or lack of space, and there are ways to make a VIA work which I'll briefly mention here, but it's always a pain in the ass to ensure that the VIA doesn't mess with the signal. If your signal is below <100MHz, then you can probably get away with using a via for that signal.

However, for higher frequencies, the via acts as a high inductance component which is not an easy path for an AC signal to take. If you want a more in depth explanation of why it's a high inductance components, then read about Loop Areas; I recommend the ".(Misc) Current Loop Areas"  from my Personal Collection list. There are also equations available that can help calculate the associated inductance and capacitance of a via based on its dimensions - refer to ".(TI) High Speed PCB Design (Applications)" in my Personal Collection list - this'll allow you to design impedance controlled vias for your signals.

Remember our talk about return currents earlier in this post? Well, what happens to the return current on the GND plane when you VIA to another signal layer?
Well, the return current would have to follow the signal to its designated GND plane so it can continue travelling on that with respect to the signal. But, the signal and return currents cannot share the same path, so the signal will go through its designated signal VIA, but the return current won't be able to go through it too to reach the other GND plane, and like it or not, that return current will find its own way there if you do not give it one. 

So, you'll just need to provide a via connecting the two GND planes together which allows for the return current to switch GND layers. A via connecting two ground planes together can be referred to as a "(GND) stitching via", so just place one of those right next to the signal via. The standard is to actually use ~4 or more GND vias and surround the signal via with them which gives the best results in terms of signal reflection. This is actually one of the biggest reasons that you should avoid POWER/GND plane stackups in high speed layouts; since it is difficult to implement stitching vias.

Now, this only works for simple cases where your two reference planes are GND planes. But in more complex PCBs, sometimes you have two different potential references (i.e. +3.3V and GND), and if you try to put a stitching via for those two planes, then you are officially a clown who just shorted their supply to GND.
So what do we do then in terms of a return via? 

This is where something called a "stitching capacitor" can be used; and it's in the name, really, it's a capacitor that prevents a DC short between the planes however provides a path for the AC return signal to continue travelling with the signal. Have a look at this short article for a bit more detail. 

4. Never create branches or protrustions (stubs) in your high frequency trace

I'm normally against yes/no rules, but this is one of those cases where unless you know exactly what you're doing, you're just going to cause yourself a headache with signal integrity and reflections all over the place. High frequency signals don't split down branches the same way a DC signal does; funnily enough you can model branches as intentionally designed inductors and capacitors - which should be enough of a red flag regarding their complexity. With a few clever tricks to minimise trace splitting, you will almost never need to branch an RF trace.

Parallel Components on RF Trace

The first trick is on how to parallel components to the RF trace without branching. Sometimes, you'll find it necessary to introduce passive circuits (i.e. LC filters) onto the trace which require parallel connections. You will need to integrate the components directly into the trace by using the component pad itself as part of the trace.

Ideally, you'll want to pick a pad size that is as close to the trace size as possible to minimise impedance mismatches between the pad and trace. So, if you have a tiny impedance controlled 6mil trace, but a 0805 capacitor pad on it, then that is awful and you're much better off downsizing the capacitor to an 0402 or even 0201 size. I'd recommend that you stick to 0402 even if it's not ideal because practically trying to soldering an 0201 component will just cause you to smash the very PCB you're assembling in anger.

Conclusion

This isn't a full list and this will probably be updated in the future as I learn more things. Some things I just can't go into since they're too dense, or aren't that important to worry about in 99% cases. So, shoo, go make fast circuit.

It goes without saying the Altium Youtube Channel is the number one place to go for all accurate PCB design content.
This is a pretty good video for beginners from a previous EEE lecturer at Sheffield that I'll link here so it isn't buried.